The following computer program listing files are submitted on a compact disc and are incorporated herein by reference:
The present invention relates generally to electronic design automation (EDA) tools. More specifically, but without limitation thereto, the present invention relates to translating a description of a circuit from a design model format into an EDA format.
In one aspect of the present invention, a method includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.